This application relates to and incorporates by reference Japanese Patent application No. 2001-29975 filed on Feb. 6, 2001.
The present invention relates to a trench gate type semiconductor device where a trench gate is formed on a silicon wafer and to a method of manufacturing a trench gate type semiconductor.
A silicon substrate including a substrate surface in a (100) plane orientation and an orientation flat in a (110) plane orientation has been used for manufacturing an insulated gate type semiconductor device such as a MOSFET, an IGBT or the like where a gate electrode is located within a trench.
In this case, since the trench of a trench gate usually has parallel side walls that are perpendicular to the orientation flat, the side walls are located in (110) planes. However, since mobility at a (110) plane is lower than that at a (100) plane, when a channel is formed at a (110) plane, the channel resistance is relatively high, which undermines the goal of reducing the ON resistance of elements.
Therefore, as explained in Japanese unexamined patent application publication (JP-A) No.H2-46716, the side wall surface of a trench gate is located in a (100) plane, which results in higher mobility, and the channel resistance is reduced, which reduces the ON resistance. This is done by using a silicon substrate having a surface in a (100) plane and an orientation flat in a (100) plane.
It is widely known that the growth rate of an oxide film is dependent on the plane orientation when a silicon oxide film is grown through thermal oxidation of silicon. Such dependence is shown in FIG. 7. As indicated by this figure, mobility is relatively high but the oxidation rate is the lowest at the plane (100). On the contrary, mobility at the planes (111) and (110) is lower than that at the plane (100) but the oxidation rate at these planes is higher.
In the trench described in unexamined patent publication (JP-A) No.H2-46716, the side walls and the trench bottom, where the channel is formed, are all located in (100) planes, thus the mobility at each plane in the trench is high and the growth rate of oxide film formed at each plane is does not vary from one surface of the trench to another.
It is preferred that the dielectric strength of a gate oxide film formed within the trench be higher at the trench bottom than that at the side walls, since the side walls are usually used to form a channel. However, when an effort is made to improve the dielectric strength of the film at the trench bottom by increasing the thickness of the film at the bottom, the thickness of the film at the side walls also increases, and the ON resistance of the element increases.
Thus, when the plane orientation is like that in unexamined patent publication (JP-A) No.H2-46716, there is an advantage with regard to the dielectric strength because the gate oxide film thickness of the side walls and the bottom, which are used as the channel, are identical due to the dependence on the plane orientation of the growth rate of the oxide film.
However, if the aspect ratio of the trench is high, for example, when the trench depth is 15 xcexcm or more, less oxidation gas is supplied to the trench bottom during thermal oxidation, and the film thickness 15 at the bottom of the side walls is less than the film thickness 14 at the area near the opening of the trench 51. Thus, the film thickness 16 at the trench bottom is relatively low as shown in the cross-sectional view of the gate oxide film 50 of FIG. 8A. In the case of an element oriented like the MOS transistor proposed in the unexamined patent publication mentioned above, the reduction of the thickness of the gate oxide film at the trench bottom part is significant because the trench gate is deeper, for example, deeper than 15 xcexcm or more, for reducing the ON resistance.
As explained above, when forming a trench gate on a silicon substrate that has a surface in a (100) plane and an orientation flat in a (110) plane, the growth rate at the bottom of the trench 51, which is in a (100) plane, is low, as shown in the cross-sectional view of the gate oxide film 50 of FIG. 8B. Thus, this arrangement is disadvantageous with regard to dielectric strength.
Considering the background above, it is an object of the present invention to provide a trench gate type semiconductor device in which the dielectric strength of a gate oxide film is higher at the trench bottom than at a pair of side walls that are used for forming a channel.
The invention is basically a trench gate type semiconductor device that includes a silicon substrate, in which semiconductor layers are formed. The silicon substrate includes a main surface and a rear surface, the rear surface being opposite to the main surface. The main surface is in a (110) plane. A trench is formed in the semiconductor layers, and the trench has at least a first pair and a second pair of opposed sidewalls, and the first pair of sidewalls are in (100) planes. A gate oxide film, which is formed by thermally oxidizing the walls of the trench, coats the surfaces of the trench. A gate electrode is located on the gate oxide film inside the trench, and channels are formed at the first pair of side walls when a predetermined voltage is applied to the gate electrode.
The invention includes a method, which basically includes preparing a silicon substrate that includes semiconductor layers. The substrate has a main surface and a rear surface. The main surface is opposite to the rear surface and is oriented in a (110) plane. The method further includes forming a trench in the semiconductor layers, such that the trench has at least a first pair and a second pair of opposed sidewalls, and the first pair of sidewalls are in (100) planes. A gate oxide film is formed by thermally oxidizing the walls of the trench. Then, a gate electrode is formed on the gate oxide film inside the trench such that channels are formed at the walls that are in (100) planes when a predetermined voltage is applied to the gate electrode.